AArch64: Add zeroing forms for predicated SVE FP-to-integer conversions
The compiler now supports zeroing predication for SVE FP-to-integer conversion instructions under SVE2.2 or SME2.2.
The compiler now supports zeroing predication for SVE FP-to-integer conversion instructions under SVE2.2 or SME2.2. A new alternative is added to patterns involving the SVE_COND_FCVTI iterator and accepting an independent value as the merge operand. The new alternative has the new zeroing-predication forms as the output string and is only enabled when sve2p2_or_sme2p2 is true in the target architecture.
In Details
SVE2.2 and SME2.2 add zeroing predication to FP-to-integer conversion instructions FCVTZU and FCVTZS. This commit modifies RTL patterns using the SVE_COND_FCVTI iterator to include a new alternative for zeroing predication, enabled when sve2p2_or_sme2p2 is true.
For Context
The Scalable Vector Extension (SVE) is an Arm architecture extension that allows vector instructions to operate on vectors of varying lengths. Predication is a feature that allows vector instructions to be conditionally executed based on a predicate vector. Zeroing predication is a form of predication where inactive lanes in the destination vector are set to zero. This commit adds support for zeroing predication to SVE FP-to-integer conversion instructions, enabled under SVE2.2 or SME2.2.