RISC-V: Use more whole-register loads and stores.
The RISC-V backend can now emit more whole-register loads and stores, improving code generation by allowing more flexible vsetvl placement.
The RISC-V backend can now split off whole-register loads and stores from pred_mov operations. Using whole-register operations avoids the need for a vtype and provides more freedom in placing vsetvl instructions. This optimization should lead to better code generation for RISC-V vector code.
In Details
This patch renames whole_reg_to_reg_move_p to whole_reg_move_p and introduces a new function whole_reg_loadstore_p in riscv-v.cc. The new function determines when to use whole-register loads/stores. Search snippets should focus on RISC-V vector extensions and vsetvl instruction.
For Context
RISC-V vector instructions operate on multiple data elements simultaneously. The vsetvl instruction configures the vector length. This commit enables the compiler to use more efficient whole-register load and store operations in certain situations. These operations don't require explicit vector length configuration, allowing the compiler to place vsetvl instructions more freely, potentially improving performance.