AArch64 introduces partial AdvSIMD vector modes.
GCC now supports partial (16- and 32-bit) AdvSIMD vector modes on AArch64 for duplication into full-sized registers.
This commit introduces new partial AdvSIMD vector modes (V4QI, V2QI, V2HI, and V2BF) for AArch64. These modes are intended for duplication into full-sized registers. The commit implements the “mov” expand and the “aarch64_simd_mov” instruction split for the new modes. It also adds aarch64_advsimd_sub_dword_mode_p to detect the new modes and disables vec_perm_const vectorization.
In Details
This patch defines new vector modes (V2QI, V4QI, V2HI, V2HF, V2BF) in aarch64-modes.def and adds a new iterator VSUB64 to iterators.md. It implements aarch64_simd_mov<mode> in aarch64-simd.md for these modes. The predicate aarch64_advsimd_sub_dword_mode_p helps classify these sub-64-bit modes. The "Da" constraint is also added to constraints.md.
For Context
AdvSIMD is a set of SIMD (Single Instruction, Multiple Data) instructions for AArch64 processors. This commit extends AdvSIMD support by introducing new, smaller vector modes. By enabling operations on smaller data types, the compiler can achieve finer-grained control over vectorization, potentially improving performance and code density.