Fix Missing Braces in riscv_rtx_costs for slli.uw Pattern
Fixes a RISC-V code generation issue where an AND case lacked braces, leading to incorrect cost calculations and potentially skipping other pattern checks.
This commit fixes a code generation issue in the RISC-V backend related to the slli.uw instruction pattern. The absence of braces in an AND case within the riscv_rtx_costs function resulted in premature termination of cost calculations. This caused the compiler to potentially skip subsequent pattern checks and fallthrough cases, affecting code generation for AND+ASHIFT combinations when specific conditions are met (TARGET_ZBA, TARGET_64BIT, and DImode).
In Details
The RISC-V backend uses riscv_rtx_costs to estimate the cost of different instruction sequences. The slli.uw pattern within this function had an AND case with a multi-statement if body lacking braces. This caused incorrect cost calculations. The fix adds the missing braces to ensure proper execution flow within the AND case.
For Context
During compilation, the compiler needs to evaluate the cost of different instruction sequences to pick the best one. This commit fixes an error in cost calculation for a specific RISC-V instruction (slli.uw) when combined with other instructions. The fix ensures that the compiler correctly assesses the cost, so it can generate the most efficient code.