AArch64: Add zeroing forms for predicated SVE integer extends
GCC now supports zeroing predication for SVE integer extension instructions on AArch64, improving code generation for SVE2.2 and SME2.2.
This commit adds support for zeroing predication to SVE integer extension instructions (SXTB, SXTH, SXTW, UXTB, UXTH, UXTW) for AArch64. This feature, available in SVE2.2 and SME2.2, allows the generation of a single zeroing-predication form of these instructions when merging with an independent value. The change modifies patterns in aarch64-sve.md and adds new tests to verify the codegen for the new zeroing variants.
In Details
This patch introduces new alternatives in aarch64-sve.md for zeroing predication of SVE integer extends, conditional upon sve2p2_or_sme2p2. It modifies the @aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode> and *cond_uxt<mode>_any patterns. The primary goal is to emit the zeroing-predication form when a const_vector of all zeroes serves as the merge operand. Toolchain devs outside the AArch64 backend might not immediately grasp the significance without familiarity with Arm's Scalable Vector Extension (SVE) and its predication features.
For Context
This commit enhances GCC's code generation for Arm's Scalable Vector Extension (SVE) on AArch64 processors. SVE is a set of CPU instructions that can operate on vectors of varying sizes, improving performance for data-parallel tasks. "Predication" allows instructions to be conditionally executed based on a boolean vector (a mask). "Zeroing predication" is a specific form where inactive vector lanes are set to zero instead of retaining their previous values. This patch adds support for new instructions that combine extending integer values with zeroing predication, available in the SVE2.2 and SME2.2 versions of the SVE specification. These new instructions can improve code efficiency when processing vector data.