RISC-V: Avoid late splitting of 64-bit vector extracts on 32-bit targets.
GCC now avoids emitting 64-bit vector extracts on 32-bit RISC-V targets, fixing a compilation failure.
When compiling for 32-bit RISC-V, GCC was emitting 64-bit vector extracts that could not be split late in the compilation process, leading to a compilation failure. This commit modifies the riscv_legitimize_move function to emit 32-bit vector extracts directly, avoiding the need for late splitting and resolving the issue.
In Details
The commit addresses a failure in reduc-6.c when compiling for 32-bit RISC-V. The problem occurs because the compiler emits a pred_extract_first instruction of a V2DImode during the legitimization of a move. Normally, this instruction would be split into two 32-bit extracts, but this splitting needs to create pseudos, which is not possible after reload. The fix ensures that 64-bit extracts are not emitted when TARGET_VECTOR_ELEN64 is false, avoiding the need for late splitting.
For Context
When compiling code that uses vectors (arrays of data) on RISC-V processors, the compiler needs to extract individual elements from those vectors. On 32-bit systems, extracting 64-bit elements from vectors can be tricky because the processor's registers are only 32 bits wide. This commit fixes an issue where the compiler was trying to perform these 64-bit extracts too late in the compilation process, leading to errors. The fix ensures that the compiler handles these extracts in a way that is compatible with 32-bit RISC-V systems.