Improve bit masking of shifted values
GCC on RISC-V now optimizes bit masking operations on shifted values, potentially reducing code size and improving performance.
The RISC-V backend in GCC can now generate more efficient code for certain bit masking operations applied to shifted values. When both upper and lower bits are masked off, and the input value is already shifted, GCC can use a shift triplet or just two shifts, reducing instruction count. This optimization improves code density and potentially enhances performance in code that uses bit manipulation.
In Details
This patch adds a new splitter in riscv.md called "masking shifted value" to optimize specific masking operations on shifted values. When masking both upper and lower bits on RISC-V, the pattern can be implemented as a shift triplet. If the input is already left-shifted and the shift count corresponds to the low mask bits, it can be further optimized into two shifts. This directly affects code generation for bit manipulation operations and reduces instruction count.
For Context
Bit manipulation is a fundamental operation in many software programs. This commit focuses on optimizing specific bit masking operations commonly used in RISC-V code. Bit masking involves isolating specific bits within a larger data value, often used in low-level programming to manipulate hardware registers or data structures. By recognizing common patterns, the compiler can replace sequences of instructions with more efficient equivalents, leading to smaller code size and faster execution.