RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx based on GR2VR cost
Combines vec_duplicate + vmsgtu.vv to vmsgtu.vx when the cost of GR2VR is zero.
This commit optimizes RISC-V vector code by combining the vec_duplicate and vmsgtu.vv instructions into a single vmsgtu.vx instruction when the cost of transferring data from general-purpose registers to vector registers (GR2VR) is zero. This optimization reduces the number of instructions executed, improving performance. The combination is skipped if the GR2VR cost is greater than zero.
In Details
This commit adds a pattern in the RISC-V backend to combine vec_duplicate followed by vmsgtu.vv into vmsgtu.vx when the GR2VR cost is zero. The change modifies predicates.md to make ltu a swappable comparison operator and adjusts riscv-v.cc to handle the swapped RTX code.
For Context
The RISC-V vector extension (RVV) allows for efficient processing of data in vector registers. The compiler attempts to optimize vector code by combining multiple instructions into a single instruction where possible. This optimization reduces the number of instructions that need to be executed, improving performance. This commit implements such an optimization for the specific case of combining vec_duplicate and vmsgtu.vv instructions.