RISC-V: Enable LMUL cost scaling for fixed-length vector modes.
The RISC-V vectorizer now applies LMUL cost scaling to fixed-length vector modes, potentially leading to the selection of smaller LMULs.
The RISC-V vectorizer now uses the same LMUL (Lane Multiplier) cost scaling for both fixed-length (VLS) and variable-length (VLA) vector modes. This encourages the vectorizer to pick smaller LMULs in some cases. Testsuite expectations have been updated to reflect these changes, and a test case relying on large LMULs has been modified to disable the vector cost model.
In Details
This commit modifies riscv-vector-costs.cc to apply LMUL cost scaling to all vector modes in the RISC-V backend. LMUL affects how vector registers are divided into lanes. The change impacts the vectorizer's cost model, influencing its decisions regarding LMUL selection during auto-vectorization. Test updates involve adjusting expected LMUL counts and disabling the cost model in a specific test case. The vectorizer pass and cost model are the primary areas of impact.
For Context
The RISC-V architecture supports vector instructions, which allow the CPU to perform the same operation on multiple data elements simultaneously. The "LMUL" (Lane Multiplier) setting determines how these vector operations are performed. This commit modifies the compiler's cost model, which estimates the performance of different code sequences. By applying LMUL cost scaling to both fixed-length and variable-length vector modes, the compiler may now choose smaller LMUL values more often. This affects the generated code and can impact the overall performance of vectorized code.