RISC-V: Add Synopsys RMX-100 series pipeline description.
Adds pipeline description for Synopsys RMX-100 series processor to the RISC-V GCC backend.
This patch introduces the pipeline description for the Synopsys RMX-100 series processor to the RISC-V GCC backend. The RMX-100 has a short, three-stage, in-order execution pipeline with configurable multiply unit options. The option -mmpy-option was added to control which version of the MPY unit the core has and what the latency of multiply instructions should be.
In Details
This commit adds a new target definition to the RISC-V backend for the Synopsys RMX-100 series processor. It defines the pipeline characteristics in arcv-rmx100.md and introduces a new option, -mmpy-option, for configuring multiply unit options. The commit also adds arcv_rmx100 to enum riscv_microarchitecture_type in riscv-opts.h and updates riscv-cores.def to include the new target. Knowledge of RISC-V target definition files and pipeline descriptions is needed.
For Context
When compiling code for a specific processor, the compiler needs to understand the processor's internal architecture, including the pipeline (the sequence of stages an instruction goes through). This commit adds support for a new processor, the Synopsys RMX-100, to the RISC-V compiler. This allows the compiler to generate code that is optimized for the RMX-100's specific characteristics, potentially improving performance.