Improve equality test of sign bit splat against zero
GCC now optimizes equality tests on RISC-V by converting sign bit splats against zero into simpler less-than/greater-than-or-equal tests.
This commit improves code generation for RISC-V, specifically targeting equality tests of sign bit splats against zero. By converting these tests into simpler less-than or greater-than-or-equal tests, the compiler avoids the need for sign bit splat operations, resulting in more efficient code. The change primarily affects RV64 due to how subregisters are handled, and a new test case verifies the optimization on both RV32 and RV64.
In Details
This patch introduces a new pattern, sign_bit_splat_equality_test, in riscv.md to optimize equality tests of sign bit splats against zero. The optimization converts these tests into simpler lt/ge tests, avoiding the sign bit splat operation. The issue was triggered by PR94892 and manifested specifically on RV64 due to the use of a lowpart SI subreg from a DI sign bit splat.
For Context
Sign bit extension is an operation that copies the most significant bit of a value to fill higher-order bits, preserving the sign of the original value when converting to a larger data type. This commit improves GCC's code generation for RISC-V processors by optimizing how the compiler handles equality checks involving sign-extended values. Specifically, it converts certain equality tests into simpler comparisons, potentially reducing the number of instructions needed and improving performance.