Enable RISC-V to generate shNadd instructions.
Improve RISC-V code generation by promoting intermediate operations from SI to DI, enabling the use of shNadd instructions.
This change promotes intermediate operations from SI (single-precision integer) to DI (double-precision integer) in certain RISC-V code patterns. This enables the generation of shNadd instructions, which combine a shift and addition, resulting in more efficient code. The patch includes a new test case and has been tested on various RISC-V configurations.
In Details
On RISC-V, this change alters code generation patterns in bitmanip.md to promote intermediate SI operations to DI when a final extending operation is present. This optimization unlocks the use of shNadd instructions, potentially reducing code size and improving performance. The transformation involves pattern matching and replacement within the instruction selection phase, targeting specific sequences of arithmetic operations.
For Context
In the compilation process, after the source code is translated into an intermediate representation (IR), the compiler selects specific machine instructions to implement the IR operations. This patch modifies the instruction selection rules for RISC-V, a family of RISC processors. It aims to generate more efficient code by recognizing opportunities to combine two operations (shift and add) into a single specialized instruction (shNadd). This optimization can improve performance by reducing the number of instructions executed.