Improve code generation for select between register and -1 on RISC-V.
GCC now generates more compact RISC-V code for conditional assignments where one branch is -1.
GCC now generates more compact code for conditional assignments where one branch assigns -1 to a register. The new sequence uses SLTI (set less than immediate) to generate 1 or 0, subtracts 1 to get 0 or -1, then ORs the result with the other input register. This reduces code size from 18 bytes to 10 bytes, which can improve performance on designs where instruction cache misses are costly. The improvement only applies to register,-1, and not const,-1 sequences.
In Details
This commit modifies ifcvt.cc to improve code generation for conditional moves where one operand is -1. The new noce_try_store_flag_logical function is called from noce_process_if_block. It uses SLTI, ADDI, and OR instructions to generate the desired result. Search terms: GCC if-conversion conditional move RISC-V
For Context
If-conversion is a compiler optimization technique that replaces conditional branches with equivalent sequences of straight-line code. This can improve performance by reducing the number of branch mispredictions, especially on architectures with deep pipelines while also reducing code size. This commit improves if-conversion for a specific pattern (conditional assignment to -1) on RISC-V, demonstrating how target-specific optimizations can further enhance code generation.