AArch64: Use fmov for some low-lane FP SIMD constant vectors.
This commit extends AArch64's AdvSIMD constant materialization to use `fmov` for vectors with a single low-element FP constant, improving code generation.
This commit extends the AArch64 backend to use the fmov instruction for materializing floating-point SIMD constant vectors where only the lowest element is a representable floating-point constant and all other elements are zero. This optimization avoids the need for more complex instructions like VDUP, leading to more efficient code generation for certain SIMD operations. The new Dc constraint is added to handle the new instruction selection.
In Details
This commit introduces new functions aarch64_output_simd_mov_imm_low and aarch64_const_vec_fmov_p in config/aarch64/aarch64.cc to handle the fmov instruction for specific SIMD constant vectors. The mov<mode> pattern in aarch64-simd.md is modified to avoid expanding these vectors into VDUP. The Dc constraint is added in constraints.md. This optimization is specific to the AArch64 architecture and its Advanced SIMD (AdvSIMD) instruction set.
For Context
SIMD (Single Instruction, Multiple Data) is a technique for performing the same operation on multiple data elements simultaneously, improving performance in many applications. Modern processors often have dedicated SIMD instruction sets. This commit optimizes the way GCC generates code for floating-point SIMD constants on AArch64 processors. By using the fmov instruction in specific cases, the compiler can generate more efficient code, especially when dealing with vectors where only the first element is a non-zero constant.