Fixes handling of IEEE min/max instructions on x86.
GCC's x86 backend now correctly handles IEEE min/max instructions, ensuring proper register usage and preventing incorrect code generation.
GCC’s x86 backend had an issue with the minmax<mode>3_4 pattern for IEEE min/max instructions, where the memory operand was incorrectly placed in the register operand position during splitting. This commit forces the relevant operand into a register to fix the issue, which prevents incorrect code generation. A new test case, gcc.target/i386/pr125308.c, validates this fix.
In Details
This commit addresses an issue in the i386 backend related to the handling of IEEE min/max instructions, specifically the *minmax<mode>3_4 pattern defined in sse.md. The problem was that the define_insn_and_split was incorrectly placing a memory operand into a register operand position, leading to incorrect code generation. Forcing the operand into a register resolves this issue. The fix is implemented in config/i386/sse.md.
For Context
In GCC, the x86 backend translates high-level code into machine instructions for x86 processors. IEEE floating-point standards define specific behaviors for min/max operations, including handling of NaN values. The compiler uses instruction patterns to recognize opportunities to use specific instructions. This change corrects an error in how one of these patterns was applied, ensuring correct code generation for floating-point min/max operations on x86 architectures.