Improve code generation for RISC-V shifts with constant counts
GCC now generates better code for RISC-V shifts with a constant count derived from a subtraction, such as ``31 - n``, by using the bitwise NOT operation.
GCC now uses the bitwise NOT operation instead of subtraction when generating code for RISC-V shifts where the shift count is expressed as 31 - n or 63 - n. This optimization avoids loading the constant (31 or 63) into a register, resulting in more compact code. The optimization is enabled when the processor implements SHIFT_COUNT_TRUNCATED semantics, meaning that only the lower bits of the shift count are relevant.
In Details
This change adds splitters to riscv.md to recognize the idiom of subtracting from 31 or 63 and then using the result as a shift count. Since RISC-V implements SHIFT_COUNT_TRUNCATED semantics but doesn't define it for "reasons", the optimization is done via splitters instead of in simplify-rtx. The core idea relies on the identity -1 - x = ~x in the truncated bitfield.
For Context
When compiling code, the compiler often needs to perform shift operations, which move the bits of a value left or right by a specified amount. Sometimes the shift amount is calculated based on other values. This commit improves code generation for a specific pattern on RISC-V processors where the shift amount is derived by subtracting from a constant. By using bitwise operations instead of subtraction, the compiler can produce more efficient machine code, improving performance and reducing code size.