Fix data type iterator for RISC-V pack RS register
This commit corrects the data type iterator used in the RISC-V `pack` instruction definition within GCC to ensure proper matching of half a target word.
The RISC-V pack instruction, defined in gcc/config/riscv/crypto.md, previously used an incorrect data type iterator for its RS register. This commit changes the iterator from HISI to HX. This ensures that the register packing logic correctly matches half a target word, which is essential for accurate code generation involving RISC-V cryptographic extensions.
In Details
Within the GCC RISC-V backend, crypto.md defines instruction patterns for cryptographic extensions. The riscv_pack instruction pattern's data type iterator for the RS register input was HISI, intended for half-word immediate/scalar, but the packing operation requires matching half a target word. Changing it to HX (half-word eXtended) correctly reflects this, aligning the instruction definition with the architectural requirements for the specific data type manipulation.
For Context
Compilers like GCC convert high-level programming code into low-level machine instructions that a processor understands. For the RISC-V processor architecture, there are specialized instructions, such as 'pack', used for cryptographic operations. These instructions often deal with specific data sizes, like half a 'word' (a standard unit of data for the processor). This change corrects a small detail in GCC's definition of the 'pack' instruction, specifically how it understands the data type of one of its input registers, ensuring that the compiler correctly handles half-word data for these specialized instructions.