RISC-V: Correct REGNO_REG_CLASS for FP hard registers.
The REGNO_REG_CLASS macro now returns the correct register class for all floating-point registers, fixing a cost model corruption in IRA.
The REGNO_REG_CLASS macro in the RISC-V backend now returns the minimal register class containing each FP hard register. Previously, some FP registers were incorrectly mapped to RVC_FP_REGS, corrupting IRA’s cost model and leading to suboptimal register allocation. This fix ensures that the cost model accurately reflects the cost of using each register, which can lead to better code generation.
In Details
This commit addresses an issue in the RISC-V backend's register allocation. REGNO_REG_CLASS maps a register number to its register class. The incorrect mapping of FP registers to RVC_FP_REGS corrupted the cost model used by IRA (integrated register allocator), specifically in setup_allocno_cost_vector. The fix involves returning FP_REGS for f0-f7 and f16-f31, and RVC_FP_REGS for f8-f15. A companion change updates riscv_secondary_memory_needed to use reg_class_subset_p. This touches the register allocation and cost model within the RISC-V backend.
For Context
In a compiler, register allocation is the process of assigning program variables to physical registers in the CPU. This is a crucial step in generating efficient machine code. The REGNO_REG_CLASS macro helps the compiler determine the type of register needed for a given variable. In the RISC-V backend, this macro was incorrectly assigning some floating-point registers to the wrong register class. This led to inaccurate cost estimations during register allocation, potentially resulting in suboptimal code. This commit fixes the macro to ensure proper register class assignment, which can lead to performance improvements.