AArch64: Add preliminary definitions for SVE2.2/SME2.2
This commit introduces preliminary definitions for SVE2.2 and SME2.2 in GCC, laying the groundwork for future SVE enhancements.
This commit prepares GCC for full SVE2.2 and SME2.2 support by adding essential definitions. It introduces TARGET_* constants based on ISA flags and new match_test definitions to control instruction pattern availability. The update also includes new effective-target checks in lib/target-supports.exp to verify SVE2.2 support in both hardware and the toolchain.
In Details
This patch introduces TARGET_* constants in aarch64.h (TARGET_SVE2p2, TARGET_SME2p2, TARGET_SVE2p2_OR_SME2p2) and match tests in aarch64.md to manage SVE2.2 and SME2.2 instruction selection. It also adds corresponding effective-target checks in lib/target-supports.exp. These definitions act as feature flags to enable/disable instruction patterns based on target architecture capabilities. Toolchain developers may overlook the significance without awareness of Arm's Scalable Vector Extension (SVE) roadmap.
For Context
This commit adds the basic building blocks for supporting new features in GCC for Arm processors. Specifically, it introduces definitions and checks for SVE2.2 and SME2.2, which are extensions to Arm's Scalable Vector Extension (SVE). SVE allows the processor to perform the same operation on multiple data elements simultaneously. The changes in this commit don't directly add new functionality, but they prepare the compiler to recognize and use instructions from these newer SVE versions when they are available on the target processor. This ensures that GCC can generate optimized code that takes advantage of the latest Arm CPU capabilities.