AVR: Use hard-reg constraints in FMUL[S[U]] instructions.
The AVR backend now uses hard register constraints for FMUL instructions, improving code generation.
The AVR backend now uses hard register constraints for FMUL, FMULS, and FMULSU instructions. This allows the compiler to generate more efficient code by restricting these instructions to specific registers. The change involves converting these instructions from expanders to insn_and_split and adding new integer attributes. This improves code generation for AVR targets when using multiplication instructions.
In Details
This commit modifies the AVR backend in config/avr/avr.md to use hard-reg constraints for the FMUL, FMULS, and FMULSU instructions. These instructions perform fractional multiplication on the AVR architecture. The change involves replacing the expander definitions with insn_and_split patterns and introducing new integer attributes and an integer iterator. This allows the compiler to have finer-grained control over register allocation for these instructions, potentially leading to better code generation.
For Context
The AVR is a family of microcontrollers widely used in embedded systems. GCC's backend for AVR translates the compiler's intermediate representation into AVR assembly code. Instruction scheduling and register allocation are critical steps in code generation that determine the order in which instructions are executed and which registers are used to store variables. By using hard register constraints, the compiler can enforce that certain instructions only use specific registers, which may be required by the architecture or ABI (Application Binary Interface). This can improve performance and reduce code size.