RISC-V: Add XuanTie C950 (xt-c9501fdvt) CPU support
Adds support for the XuanTie C950 (xt-c9501fdvt) RISC-V CPU in GCC.
This commit adds support for the XuanTie C950 (xt-c9501fdvt) RISC-V CPU to GCC. The C950 is based on the rva23s64 profile and includes additional extensions. The changes include adding the CPU to the list of known RISC-V CPUs, regenerating documentation, and adding a new test case.
In Details
This commit adds a new RISC-V core definition to riscv-cores.def. The XuanTie C950 is based on the rva23s64 profile with additional extensions. The riscv-cores.def file defines the known RISC-V cores and their associated tuning parameters. This impacts code generation by allowing GCC to select appropriate instruction scheduling and other optimizations for the C950.
For Context
RISC-V is a modular open-source instruction set architecture (ISA). GCC needs to be configured to support specific RISC-V processors. This commit adds support for the XuanTie C950, a specific RISC-V processor implementation, allowing GCC to generate optimized code that takes advantage of the C950's unique features.