RISC-V: Remove interleaved vector synthesis optimization [PR125215]
The "hi/lo" optimization path for interleaved stepped constant vector synthesis in RISC-V has been removed due to performance concerns.
The commit removes the “hi/lo” optimization in interleaved stepped constant vector synthesis for RISC-V. This optimization was found to be less effective than the fallback merge version, especially after addressing overflow issues. The associated tests have also been removed.
In Details
This commit removes expand_const_vector_interleaved_stepped_npatterns's hi/lo optimization path in riscv-v.cc. The change simplifies vector synthesis and removes obsolete tests (slp-interleave-[1-5].c). The removed optimization aimed to improve the generation of interleaved stepped constant vectors, but proved less effective than the merge fallback.
For Context
This commit concerns vectorization, which is an optimization technique where scalar operations are replaced with vector operations that process multiple data elements simultaneously. This change specifically impacts the RISC-V architecture's vector extension. The optimization attempted to generate efficient code for specific patterns of vector initialization, but was ultimately detrimental to performance.