Add RISC-V test cases for scalar unsigned SAT form 10.
This commit adds new test cases for scalar unsigned SAT form 10 in the RISC-V architecture.
This commit adds test cases for scalar unsigned SAT form 10 to the RISC-V architecture. The added tests ensure the correct behavior of this form, which is already supported. These tests enhance the coverage of the RISC-V instruction set and help ensure the reliability of code compiled for this architecture.
In Details
This commit introduces new test cases for RISC-V scalar unsigned SAT form 10, extending the existing test suite in gcc.target/riscv/sat/. Scalar SAT instructions perform arithmetic operations with saturation, preventing results from overflowing. The tests cover various data types (u16, u32, u64, u8) and scenarios. While seemingly localized, changes to the test suite can reveal subtle issues in code generation or instruction selection.
For Context
This commit adds new tests for the RISC-V architecture, specifically for operations involving scalar unsigned saturated arithmetic. RISC-V is a modern open-source instruction set architecture (ISA) used in various processors. Saturated arithmetic prevents overflow by capping results at a maximum or minimum value, instead of wrapping around. These tests validate that the compiler correctly generates code for these operations across different data sizes, ensuring more robust software.