AArch64: Add zeroing forms for predicated SVE bit reversal operations
The compiler now supports zeroing predication for SVE bit reversal operations under SVE2.2 or SME2.2.
The compiler now supports zeroing predication for SVE bit reversal operations under SVE2.2 or SME2.2. This change adds an alternative for the zeroing-predication forms of the original instructions. The pattern for REVD also required changes to the predicate for operand 3 to accept constant zero RTX whenever SVE2.2 is enabled, and uses the /z form of the REVD instruction for PRED_X predication to save a data dependency.
In Details
SVE2.2 and SME2.2 add zeroing predication to bit reversal operations like REVB, REVH, REVW and REVD. This commit adds an alternative for the zeroing-predication forms of the original instructions in aarch64-sve.md and aarch64-sve2.md. The pattern for REVD also uses the /z form of the REVD instruction for PRED_X predication to save a data dependency.
For Context
The Scalable Vector Extension (SVE) is an Arm architecture extension that allows vector instructions to operate on vectors of varying lengths. Predication is a feature that allows vector instructions to be conditionally executed based on a predicate vector. Zeroing predication is a form of predication where inactive lanes in the destination vector are set to zero. This commit adds support for zeroing predication to SVE bit reversal operations, enabled under SVE2.2 or SME2.2.