RISC-V: Add test for vec_duplicate and vmsgt.vv combine
This commit adds a new test case to verify the combining of vec_duplicate and vmsgt.vv instructions into vmsgt.vx on RISC-V.
This commit adds a new test case for the RISC-V vector extension to verify the combination of vec_duplicate and vmsgt.vv instructions into a single vmsgt.vx instruction. The test checks the generated assembly code when the cost of moving data from a general-purpose register to a vector register (GR2VR) is 0, 1, and 15. This ensures that the compiler correctly performs this optimization under different cost scenarios.
In Details
This patch adds a test case to gcc.target/riscv/rvv/autovec/vx_vf/ to verify the combination of vec_duplicate and vmsgt.vv into vmsgt.vx. The combination depends on the cost of GR2VR, and the test checks cases where the cost is 0, 1, and 15. The test suite uses helper macros and data from vx_binary.h and vx_binary_data.h.
For Context
This commit adds a test case for RISC-V vector instruction optimization. Vector instructions allow the processor to perform the same operation on multiple data elements simultaneously. The compiler can often combine multiple simpler instructions into a single, more efficient instruction. This commit specifically tests the combination of instructions that involve duplicating a vector and then comparing it to another vector (vmsgt.vv) into a single instruction (vmsgt.vx) that directly compares a vector with a scalar value. The test verifies that this optimization is done correctly, taking into account the cost of moving data between different types of registers.