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JUNE 15, 2026
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gcc Performance Win

Simplify RTL bit-flipping operations to use XOR

The compiler can now simplify certain bit-flipping RTL patterns into XOR operations, improving code generation for RISC-V and potentially other architectures.

The compiler can now recognize and simplify RTL patterns that flip specific bits in a register. The optimization applies when the RTL code uses IOR, AND, and NOT operations with constants to isolate and flip a bit. This change improves code generation on RISC-V and may benefit other targets, especially those with sub-word arithmetic. The simplification rewrites the code to use a single XOR operation.

In Details

This patch simplifies RTL representing bit-flipping operations into XORs. It targets specific patterns involving IOR, AND, and NOT operations on registers with constant masks. The primary focus is on cases where the same register appears in both arms of the IOR, and the constants isolate the bit being flipped. While the initial motivation stems from RISC-V (PR80770), the simplification also covers a sub-word arithmetic case seen on H8. search_context returned: [].

For Context

Compilers often represent operations in Register Transfer Language (RTL) before generating machine code. RTL describes how data moves between registers and memory, and how it's transformed along the way. This commit focuses on simplifying certain RTL patterns that perform bitwise operations to flip specific bits within a register. By recognizing these patterns and transforming them into equivalent XOR operations, the compiler can generate more efficient machine code. search_context returned: [].

Filed Under: optimizationRISC-Vcode generationRTL