Improve code for (1 << N) & 0x1 on RISC-V.
A RISC-V-specific code splitter improves the generated assembly for the expression (1 << N) & 0x1.
The RISC-V backend now generates more efficient code for expressions of the form (1 << N) & 0x1 on RV64. A new code splitter handles the case of a 32-bit shift on RV64. The optimization masks the shift count to sanitize it, generating two instructions: andi and seqz instead of li, sllw, and andi.
In Details
This commit introduces a RISC-V-specific code splitter to improve the code generated for the expression (1 << N) & 0x1. The change focuses on the RV64 architecture and specifically addresses the case where a 32-bit shift is involved. This optimization occurs at the RTL level. The rationale for not addressing this in simplify-rtx is the complexity of SHIFT_COUNT_TRUNCATED, mode handling for shift counts, and subregs.
For Context
When compiling code, GCC performs various optimizations to improve the efficiency of the generated machine code. This commit focuses on improving the code generated for a specific bit manipulation pattern on RISC-V processors. Specifically, it optimizes the expression (1 << N) & 0x1, where N is a variable. This pattern involves left-shifting the value 1 by N bits and then performing a bitwise AND with 1 to extract the least significant bit.