aarch64: Add SME_MOP4 intrinsics and instructions
Adds support for new SME_MOP4 instructions and intrinsics for aarch64.
This commit introduces support for the +sme-mop4 extension on aarch64 by adding corresponding intrinsics and instructions. It includes definitions for various svmop4a variants with different data types and configurations, as well as new SVE mode suffixes and register constraints. The changes also update internal functions to handle new register classes and function shapes.
In Details
Support for the ARM Scalable Matrix Extension (SME) +sme-mop4 feature is extended by adding new intrinsics and their corresponding machine instructions in the aarch64 backend. This involves defining new function shapes for mop4 operations, updating register class handling for high-precision floating-point registers (FP_HI_REGS), and enabling the correct predefines for the __ARM_FEATURE_SME_MOP4 macro.
- SME
- Scalable Matrix Extension, an ARM architecture extension for high-performance matrix operations.
- SVE
- Scalable Vector Extension, an ARM architecture extension for vector processing with variable vector lengths.
- intrinsics
- Special functions that map directly to hardware instructions, providing low-level control.
- register constraints
- Rules in the compiler that specify which registers can be used for specific operands in assembly instructions.