RISC-V: Add test cases for vwmulsu.vv register overlap
New test cases verify the correct handling of register overlap for the RISC-V vwmulsu.vv instruction, particularly when overlap is enabled.
This commit adds a suite of test cases to validate the RISC-V Vector extension’s vwmulsu.vv instruction. The tests specifically focus on scenarios involving register group overlap, ensuring that the compiler correctly handles these situations when overlap is enabled. The goal is to ensure the instruction’s behavior aligns with its specification, especially concerning register allocation and usage.
In Details
This commit adds test cases for the vwmulsu.vv instruction within the RISC-V Vector (RVV) extension. It specifically targets the group_overlap functionality, ensuring that the compiler correctly generates code for this instruction when register group overlap is enabled. This is crucial for verifying the correctness of the vectorizer and code generation for complex vector operations that might reuse registers.
- vwmulsu.vv
- A RISC-V Vector extension instruction for performing a widening multiply-accumulate operation on unsigned integers, with both source operands and the destination in vector registers.
- RVV
- RISC-V Vector extension, a set of instructions designed to perform SIMD (Single Instruction, Multiple Data) operations on vectors of data.
- register overlap
- A feature in some vector instruction set architectures where vector registers can be used in a way that allows subsequent operations to reuse parts of previously used registers, potentially improving efficiency.