ifcvt handles targets without scheduling models; adds RISC-V tests.
ifcvt now supports targets lacking scheduling models and includes new RISC-V tests for cost analysis.
This commit enhances the if-conversion (ifcvt) functionality by enabling it to handle targets that do not have explicit scheduling models. For such targets, m68k_sched_issue_rate now safely returns 1 instead of triggering an error. Additionally, new test cases have been added for the RISC-V architecture to evaluate if-conversion costs on both single-issue and multi-issue processors.
In Details
The if-conversion (ifcvt) pass in GCC relies on scheduling information to accurately cost predicated operations. Targets without a dedicated scheduling model, such as some configurations of m68k, could previously cause m68k_sched_issue_rate to call gcc_unreachable. This change modifies m68k_sched_issue_rate to return 1 for targets lacking a scheduling model, preventing this crash. New tests are introduced for RISC-V to cover scenarios with different issue rates, aiding in the validation of ifcvt's cost model on diverse architectures.
- ifcvt
- If-conversion. A compiler optimization pass that transforms conditional control flow (if-then-else structures) into conditional instructions, where supported by the target architecture. This can improve performance by reducing branch penalties.
- Scheduling model
- A component within a compiler backend that models the execution characteristics of a target processor's instruction pipeline. It helps the compiler make optimal instruction ordering decisions, considering factors like instruction latency, throughput, and resource conflicts.
- m68k_sched_issue_rate
- A function specific to the m68k (Motorola 68k) processor backend that likely returns the number of instructions the processor can issue per clock cycle, based on its scheduling model.
- gcc_unreachable
- A GCC internal macro or function indicating a point in the code that should logically never be reached. If executed, it typically signals a bug in the compiler.
- RISC-V
- An open-standard Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing principles. It is designed to be simple, modular, and extensible.
- Single-issue / Multi-issue
- Describes a processor's ability to execute instructions. A single-issue processor can execute only one instruction per clock cycle, while a multi-issue processor can execute multiple instructions concurrently.