aarch64: Use register number for SUBS predicate
aarch64 SUBS instruction predicate now checks register numbers directly, fixing issues with SME2 and GENERAL_REGS.
The predicate aarch64_general_reg, used to fuse comparison and subtraction into the SUBS instruction, has been modified. Previously, it relied on REGNO_REG_CLASS, which incorrectly reported subclasses for registers x8-x15 when SME2 support was enabled. The predicate now directly tests the register number, ensuring SUBS instructions are correctly generated even when their destination is in these registers, while still rejecting the stack pointer as intended.
In Details
The aarch64_general_reg predicate in predicates.md was updated to fix a regression introduced by SME2 support. Previously, it used REGNO_REG_CLASS to check if a register belonged to GENERAL_REGS. However, REGNO_REG_CLASS returns subclasses like W8_W11_REGS for x8-x15, causing the predicate to fail. The change modifies it to directly check the register number, ensuring that peephole2 patterns fusing comparisons and subtractions into SUBS correctly target registers x8-x15 when they are allocated to GENERAL_REGS, while preserving the rejection of the stack pointer.
- SUBS
- An ARM instruction that subtracts one register from another and sets the condition flags.
- aarch64
- The 64-bit ARM architecture.
- GENERAL_REGS
- A register class typically encompassing the general-purpose registers available on a CPU.
- REGNO_REG_CLASS
- A GCC internal mechanism that returns the register class a given register number belongs to.
- SME2
- Scalable Matrix Extension 2, an advanced feature for the Arm architecture that provides enhanced matrix processing capabilities.