Allow RISC-V 't' registers in scan-assembler tests
Expands RISC-V assembly tests to include 't' registers for better coverage.
This commit updates RISC-V scan-assembler tests to allow the use of ‘t’ registers, which were previously excluded. The change broadens testing coverage by ensuring that assembly directives and register aliases are correctly handled across different RISC-V core configurations, particularly on the K1 design. This addresses a potential oversight in register alias handling that could lead to test failures.
In Details
In the RISC-V target, scan-assembler tests verify the correct interpretation of assembly mnemonics and register usage. This change modifies test directives to include 't' registers, which are part of the general-purpose register set. Previously, the tests might have only considered 'a' and 'x' register aliases, leading to false positives or negatives when 't' registers were utilized by the compiler, especially with newer CPU designs like the K1 that leverage these registers.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computer principles. It is designed to be simple, modular, and extensible.
- scan-assembler
- A testing utility used to verify that generated assembly code matches expected patterns and register usage.
- register alias
- An alternative name or symbolic representation for a hardware register, allowing for different programming abstractions.
- RVV
- RISC-V Vector extension, providing support for SIMD (Single Instruction, Multiple Data) operations.