Optimize two-element vector lane copies on AArch64
Eliminates unnecessary register moves for two-element vector lane copies, fixing a performance regression.
This commit resolves a performance regression on AArch64 where copying lanes in two-element vectors resulted in an extra register move instruction. By adding new patterns that correctly tie the destination register to the appropriate input, the compiler now generates more efficient code, reducing instructions from two to one for these operations.
In Details
The AArch64 NEON vectorizer previously suffered a regression (PR123951) where vec_extract/vec_set idioms for two-element vector lane copies were folded into VEC_PERM_EXPR. The constant permute expander's patterns incorrectly tied the result to one input, forcing the register allocator to insert a move. New patterns in aarch64-simd.md (aarch64_simd_vec_set_lane0 and aarch64_simd_vec_copy_lane_same) address this by providing alternatives that tie the destination to the correct input, thus avoiding the extra move.
- AArch64
- The 64-bit ARM architecture.
- NEON
- ARM's Advanced SIMD (Single Instruction, Multiple Data) extension, providing advanced vector processing capabilities.
- VEC_PERM_EXPR
- An intermediate representation expression in GCC used for vector permutation operations.
- Register allocator
- A compiler component responsible for assigning program variables to machine registers to optimize performance.