aarch64: Implement CTZ for Advanced SIMD byte and halfword modes
New AArch64 Advanced SIMD instructions for count trailing zeros (CTZ) improve performance for byte and halfword operations.
The AArch64 backend now implements the ctz2 instruction for Advanced SIMD’s byte and halfword modes. Previously, these modes were expanded into a less efficient generic sequence involving bit reversal, AND, CLZ, and subtraction. The new implementation directly uses RBIT and REV16 where appropriate, reducing the instruction count and eliminating the need for vector constants. This leads to faster execution for bitwise operations involving trailing zeros in these data types.
In Details
This patch introduces dedicated expanders in aarch64-simd.md for ctz<mode>2 targeting VDQ_BHSI (vector doubleword, quadword, byte, halfword, singleword, integer) types. Previously, byte (VB) and halfword (VS) modes for ctz<mode>2 were expanded using a generic sequence that required multiple instructions and constants. The new implementation folds these into a single expander, leveraging RBIT for byte reversal and REV16 for halfword adjustments before applying CLZ. This is efficient because RBIT reverses bits within each byte, and for halfwords, REV16 positions the bytes correc…
- CTZ
- Count Trailing Zeros. An instruction that returns the number of zero bits following the least significant one bit in a binary number.
- Advanced SIMD
- ARM's Single Instruction, Multiple Data (SIMD) architecture extension, also known as NEON, for accelerated multimedia and signal processing.
- AArch64
- The 64-bit execution state of the ARMv8-A architecture.
- RBIT
- Reverse bits. An instruction that reverses the order of bits within each byte of a register.
- REV16
- Reverse elements of 16 bits. An instruction that reverses the order of bytes within each 16-bit halfword of a register.