RISC-V: Allow register overlap for vwmacc[u].vv instructions.
Enables register group overlap for RISC-V vwmacc and vwmaccu vector instructions, improving scheduling flexibility.
This change allows the RISC-V vector instructions vwmacc.vv and vwmaccu.vv to utilize register group overlap. Similar to other vector instructions like vwadd.vv and vwmul.vv, this relaxation in register constraints provides the compiler with more flexibility in scheduling and register allocation, potentially leading to improved performance by enabling more efficient use of the vector register file.
In Details
This commit (2be327c50de607ab0d8c1a2295160313c7edf6db) modifies the vector.md file in GCC's RISC-V backend to permit register group overlap for the vwmacc.vv and vwmaccu.vv instructions. This aligns their register usage semantics with other vv-type widening instructions, enabling tighter instruction scheduling and potentially better register pressure management. The 'Wvr' constraint is leveraged to achieve this.
- vwmacc.vv
- A RISC-V vector instruction for a 2x16-bit to 32-bit multiply-accumulate operation, operating on vector registers.
- vwmaccu.vv
- A RISC-V vector instruction for a 2x16-bit to 32-bit unsigned multiply-accumulate operation, operating on vector registers.
- register group overlap
- A condition in RISC-V vector operations where the destination register group for an instruction might overlap with the source register group, requiring careful handling by the compiler and hardware.
- RISC-V Vector Extension (RVV)
- A set of instructions for the RISC-V architecture that enable efficient processing of vector and matrix data, crucial for high-performance computing and scientific applications.
- Wvr constraint
- A constraint in GCC's target description files (like vector.md) that specifies requirements for vector registers, often related to their size or specific capabilities.