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OCTOBER 6, 2026
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gcc/aarch64 Performance Win

aarch64: Add SME2.1 structured sparsity outer product intrinsics

Adds support for new AArch64 SME2.1 structured sparsity outer product intrinsics.

This commit introduces support for several new AArch64 Scalable Matrix Extension (SME) version 2.1 structured sparsity outer product intrinsics. These intrinsics, requiring the +sme-tmop and various +sme-f* or +sme-b* architecture options, enable specialized matrix operations for sparse data. The changes include adding new intrinsic shapes, register constraints, and predicates to the compiler, along with associated tests and documentation updates.

In Details

This patch adds support for a set of new AArch64 SME2.1 intrinsics, specifically targeting structured sparsity outer products. These intrinsics operate on SME tile registers (ZA) and require specific SME feature flags like FEAT_SME_TMOP, FEAT_SME_F8F16, etc. New intrinsic shapes (ternary_za_uint_dual_single), a new register constraint for ZA tile elements, and updated instruction patterns in aarch64-sme.md are introduced. The svtmopa_lane_za intrinsic implementation is added to svtmopa_lane_za_impl within aarch64-sve-builtins-sme.cc.

For Context
AArch64
The 64-bit ARM architecture.
SME
Scalable Matrix Extension, an ARM architecture feature for accelerating matrix operations using vector processing.
SME2.1
Version 2.1 of the ARM Scalable Matrix Extension, introducing new features and instructions.
intrinsics
Special functions that map directly to specific hardware instructions, providing a C/C++ interface to low-level operations.
structured sparsity
A data structure or format that optimizes storage and computation for matrices containing many zero elements.
outer product
A matrix operation where two vectors are multiplied to produce a matrix.
ZA tile
A register within the ARM SME architecture used to store matrix tiles for computations.
predicate
A condition or test used in the compiler's machine description to determine if a particular instruction pattern is valid for the target architecture and current configuration.
Filed Under: gccaarch64SMEintrinsicsvector processing