RISC-V: Allow RVV register overlap for vwmaccsu.vx
RISC-V vwmaccsu.vx instruction now supports register overlap, similar to other widen ternary instructions.
This change extends the support for register overlap to the RISC-V vwmaccsu.vx instruction. By leveraging the Wvr constraint in the vector-masking table, this modification aligns the behavior of vwmaccsu.vx with similar instructions like vwmacc[u].vx, allowing for more flexible and potentially optimized register usage.
In Details
This commit modifies the RISC-V vector instruction backend to allow register overlap for the vwmaccsu.vx instruction. It achieves this by utilizing the Wvr (widening vector register) constraint in the vector.md table. This enables the instruction to reuse registers that might be considered overlapping in certain widening operations, consistent with the handling of vwmacc[u].vx.
- vwmaccsu.vx
- A RISC-V Vector Extension instruction that performs a vector-wide-multiply-accumulate operation with signed-to-unsigned widening and a vector-masking element. The
.vxsuffix indicates that the second source operand is a vector register. - Wvr constraint
- In GCC's machine description files (e.g.,
vector.md), a constraint that specifies when a vector register can be used as a destination register in an operation that involves widening or a similar transformation, allowing for register reuse.