RISC-V: Allow RVV register overlap for vwmulsu.vx
Enables register overlap for RISC-V `vwmulsu.vx` instruction.
This commit allows register overlap for the RISC-V vector instruction vwmulsu.vx. Similar to other widening vector multiplication instructions, this change enables the reuse of vector registers, which can lead to more efficient code generation. The change modifies the vector constraint in the GCC target configuration for RISC-V.
In Details
Modifies gcc/config/riscv/vector.md to allow register overlap for the vwmulsu.vx instruction by leveraging the Wvr constraint. This change is analogous to similar support added for vw{add,sub,mul}[u].vx, enabling more flexible and potentially efficient code generation by allowing the destination register to overlap with source registers in this dual-widen-vx instruction.
- RVV
- RISC-V Vector extension. A set of instructions for performing SIMD (Single Instruction, Multiple Data) operations on vectors of data.
- vwmulsu.vx
- A RISC-V vector instruction for unsigned widening multiplication of a vector register by a scalar from another vector register.
- register overlap
- In the context of RISC-V vector operations, this refers to a scenario where destination and source registers in an instruction might partially or fully overlap, requiring careful handling by the compiler to maintain correctness.
- Wvr constraint
- A GCC machine mode constraint for RISC-V vector instructions that permits register overlap, specifically for widening operations.
- vector.md
- A GCC machine description file for the RISC-V target that defines vector instructions and their properties.