RISC-V: Add test cases for vwmaccu.vx register overlap.
New RISC-V tests cover register group overlap for vwmaccu.vx.
This commit adds a comprehensive suite of test cases for the vwmaccu.vx instruction on RISC-V, specifically focusing on register group overlap scenarios. The tests cover various data types and vector lengths to ensure the correct handling of register allocation and usage during autovectorization.
In Details
A significant number of test cases have been added to the RISC-V testsuite (gcc.target/riscv/rvv/autovec/group_overlap/) for the vwmaccu.vx instruction. These tests specifically target scenarios involving register group overlap across different data types (u16, u32, u8) and mask/fractional elements (m1, m2, m4, mf2, mf4, mf8). This aims to ensure correct autovectorization and register allocation when these instructions are used in potentially overlapping register groups.
- vwmaccu.vx
- A RISC-V vector instruction that performs an unsigned wide multiply-accumulate operation with a vector register and a scalar element.
- register group overlap
- A situation in vector processing where multiple vector operations might need to use the same set of registers, requiring careful management to avoid data corruption or incorrect results.
- autovectorization
- The process by which a compiler automatically transforms scalar code into vector code to take advantage of SIMD (Single Instruction, Multiple Data) instructions.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computer principles.