aarch64: let the negated 64-bit compare take a zero in the general registers
Aarch64's 64-bit comparison optimization now correctly handles comparisons against zero using general-purpose registers, avoiding inefficient vector register m…
This commit improves the aarch64 backend by allowing the negated 64-bit comparison instruction (aarch64_cm<optab>di) to accept a zero operand directly in general-purpose registers. Previously, comparing against zero required moving the value through a vector register, which was less efficient. This change optimizes code like -(long) (x == 0) by using a general register comparison, reducing cross-register-file moves and improving performance.
In Details
The aarch64_cm<optab>di instruction pattern in gcc/config/aarch64/aarch64-simd.md is updated to accept a zero constant as the second operand in its general register alternative. Previously, this alternative only accepted a register, forcing zero comparisons to use less efficient vector register paths. The aarch64_gen_compare_reg helper, used by the split, already handles zero operands correctly, simplifying the change. This optimization is beneficial for constant-time code, as seen in libraries like OpenSSL.
- aarch64
- The 64-bit ARM architecture. GCC supports generating code for this widely used processor architecture.
- general registers
- The primary set of registers available on a CPU, used for arithmetic, logic, and data manipulation operations. In contrast to special-purpose registers like program counters or status registers.
- vector registers
- Specialized registers used for SIMD (Single Instruction, Multiple Data) operations, allowing a single instruction to operate on multiple data elements simultaneously. These are distinct from general-purpose registers.
- optab
- An 'operation table' in GCC, which maps RTL (Register Transfer Language) operations to specific machine instructions.
- SIMD
- Single Instruction, Multiple Data. A class of parallel computers in Flynn's taxonomy that perform the same operation on multiple data points simultaneously. Aarch64 has its own SIMD instruction set (NEON).