Adjust more RISC-V tests
Updates expected outputs for several RISC-V tests due to minor changes in generated code.
This commit adjusts the expected outputs for a number of RISC-V test cases in the GCC test suite. A recent generic change in the compiler subtly altered the generated assembly code for various tests. After reviewing these changes and confirming their validity from a code generation perspective, the expected outputs in the test suite have been updated to match the new behavior, ensuring the test suite remains accurate.
In Details
Following a generic compiler change that introduced subtle alterations in RISC-V code generation, the expected outputs for several gcc.target/riscv/rvv/autovec/sat and gcc.target/riscv/rvv/base tests have been modified. These adjustments reflect sensible code generation improvements and ensure test suite integrity.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computer principles. It is designed to be simple, modular, and extensible.
- rvv
- RISC-V Vector extension. A set of instructions for performing SIMD (Single Instruction, Multiple Data) operations on vectors of data, significantly boosting performance for data-parallel tasks.
- Test suite
- A collection of test cases designed to verify the correctness and functionality of a software system, in this case, the GCC compiler for the RISC-V architecture.
- Autovec
- Refers to automatic vectorization, a compiler optimization technique that transforms scalar code into vector instructions to exploit data-level parallelism.
- Generated output
- The code or data produced by a compiler or tool. In this context, it refers to the assembly code or machine code generated by GCC for RISC-V targets.