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OCTOBER 6, 2026
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aarch64 Performance Win

aarch64: Use SVE2 SQXTNB and UQXTNB for saturating truncation

Vectorization of saturating truncation operations improved for aarch64 using new SVE2 instructions.

GCC now leverages SVE2 SQXTNB and UQXTNB instructions on aarch64 for saturating truncation operations, enhancing vectorization. Previously, these operations were emulated less efficiently using minimum and maximum instructions followed by a truncating store. This change improves performance by directly using hardware support for these operations, making code generation more efficient for saturated truncation patterns.

In Details

The vect_recog_sat_trunc_pattern was extended to recognize saturating truncation operations on SVE2 modes. This was achieved by introducing new patterns that utilize the SQXTNB and UQXTNB instructions, which provide hardware support for saturating truncation. These instructions operate on SVE vector registers, halving the element width while saturating. The change also ensures that the NARROW_CLIP form of .SAT_TRUNC is now reachable on aarch64, improving code generation for saturation and truncation scenarios.

For Context
SVE2
Scalable Vector Extension 2, an advanced set of SIMD (Single Instruction, Multiple Data) instructions for ARM processors that allows for vectors of varying lengths.
SQXTNB
Saturate and truncate signed integer, lower half. This SVE2 instruction saturates values in the source vector to the signed range of the destination element width and then truncates them to the lower half of the elements.
UQXTNB
Saturate and truncate unsigned integer, lower half. Similar to SQXTNB but for unsigned integers.
vectorization
The process of transforming a loop or algorithm to operate on multiple data elements simultaneously using SIMD instructions, often leading to significant performance improvements.
optab
A table of operations, used by GCC to represent machine-specific operations for different data types and modes.
unspec
An internal GCC representation for machine-specific operations that do not have a direct equivalent in the generic intermediate representation.
Filed Under: aarch64vectorizationSVE2optimization