Only support GFNI V32QImode rotates with AVX2, not just AVX
GFNI rotates on V32QImode now correctly require AVX2, preventing ICEs.
This commit corrects the CPU feature requirements for GFNI V32QImode rotates. Previously, these operations were incorrectly enabled with just AVX, leading to compiler internal errors (ICEs) because AVX alone does not support the necessary V32QImode shifts. The change mandates AVX2, aligning with the actual hardware capabilities and resolving PR127498.
In Details
The rot{l,r}v32qi optab in sse.md was conditioned on TARGET_GFNI && TARGET_AVX. However, the underlying V32QImode shifts required by the fallback expansion (bitwise or of two shifts) are only available with AVX2. This commit adds TARGET_AVX2 to the condition, ensuring that these operations are only used when supported, thus fixing PR127498.
- GFNI
- GFNI (GFNI) instructions provide efficient operations for Galois Field arithmetic, often used in cryptography and error correction codes.
- V32QImode
- A SIMD mode representing 32 packed single-byte integers (8-bit integers).
- AVX
- Advanced Vector Extensions, a set of CPU instructions that extend the capabilities of SSE with wider vector registers and new operations.
- AVX2
- An enhancement to AVX, adding more instructions and supporting wider integer operations.
- ICE
- Internal Compiler Error, a crash within the compiler itself, usually indicating a bug in the compiler's logic.
- optab
- An "operation table" that maps general operations (like rotate, add, multiply) to specific machine instructions for a target architecture.