RISC-V: Enable autoprefetcher modeling
Adds basic support for modeling RISC-V hardware autoprefetchers to improve code scheduling.
This commit introduces initial support for modeling hardware autoprefetchers on RISC-V processors, similar to the existing AArch64 model. It enables weak autoprefetcher modeling and sets up tuning parameters, preparing for more advanced modeling of strong autoprefetchers in future work, which is beneficial for scheduling store instructions on relevant hardware.
In Details
This change extends the RISC-V backend by adding a new tuning parameter struct riscv_tune_param::xt_c9501_tune_info to model the behavior of hardware autoprefetchers. Initially, it supports AUTOPREFETCHER_OFF and AUTOPREFETCHER_WEAK modes, deferring the AUTOPREFETCHER_STRONG model until max_issue support is complete. The riscv_override_options_internal function now uses the autoprefetcher model to set param_sched_autopref_queue_depth, influencing instruction scheduling for models like the C9501, which benefit from sorted store instructions.
- autoprefetcher
- A hardware mechanism in some processors that automatically fetches data from memory into the cache before it is explicitly requested by the CPU. This can improve performance by reducing memory latency.
- RISC-V
- An open-standard instruction set architecture (ISA) based on Reduced Instruction Set Computer principles, designed to be simple, modular, and extensible.
- instruction scheduling
- The process by which a compiler or processor reorders instructions to optimize performance, for example, by hiding memory latencies or improving pipeline utilization.
- store instructions
- CPU instructions that write data from a processor register to a location in memory.