Support BSR0 register
Adds support for the BSR0 register, treating it similarly to TMM registers for future extensibility.
This commit introduces support for the BSR0 register, part of the ACEv1 ISA. It treats BSR registers similarly to TMM registers, allocating space for future extensions and enabling register allocation. Changes include updates to register class maps, debugger register maps, conditional register usage, and machine description files, ensuring the BSR0 register is recognized and managed by the compiler.
In Details
Adds support for the BSR0 register within the i386 backend. regclass_map, debugger_register_map, and HI_REGISTER_NAMES are updated to include BSR registers. ix86_conditional_register_usage is modified to enable BSR when ACE is present. FIXED_REGISTERS and CALL_USED_REGISTERS are updated for BSR0. The machine description (i386.md) introduces BSR0_REG, and predicates.md adds bsr0_operand for register matching.
- ACEv1
- AI Compute Extensions version 1, a new x86 instruction set architecture designed for AI and compute-intensive workloads.
- BSR0
- The first Block Scale Register (BSR) in the ACEv1 ISA, likely used for scaling operations.
- TMM
- Tile Matrix Multiply registers, used in AMX (Advanced Matrix Extensions) for matrix operations.
- register allocation
- The process by which a compiler assigns program variables and temporary values to the limited number of hardware registers available on a CPU.