aarch64: Fix invalid CSE on read FFRs in SVE builtins.
Corrected how FFR values are updated in AArch64 SVE builtins to prevent incorrect Common Subexpression Elimination.
This fix addresses an issue in AArch64 SVE builtins where the FFR (First Fault Register) update was not correctly dependent on the loaded value, leading to invalid Common Subexpression Elimination (CSE). The changes modify the expand methods for svldff1_gather_impl, svldff1_gather_extend, svldxf1_impl, and svldxf1_extend_impl, and update the aarch64_update_ffr_for_load pattern in aarch64-sve.md to ensure the FFR update is based on the actual loaded data, thus fixing the PR126629.
In Details
The expand methods for AArch64 SVE load builtins (svldff1_* and svldxf1_*) have been modified to correctly handle the First Fault Register (FFR) update. Previously, the update logic might have been reordered or eliminated incorrectly by CSE if it didn't directly depend on the loaded value. This patch ensures the FFR update is tied to the load operation itself, resolving an issue reported in PR target/126629, and updates the corresponding aarch64_update_ffr_for_load pattern.
- FFR (First Fault Register)
- A register used in AArch64's Scalable Vector Extension (SVE) to track the status of memory operations, particularly for faulting behavior in gather/scatter operations.
- SVE
- Scalable Vector Extension. An advanced vector processing instruction set for ARM architectures, allowing for variable vector lengths.
- CSE (Common Subexpression Elimination)
- An optimization technique where the compiler identifies identical expressions computed multiple times and replaces subsequent computations with the result of the first one.
- aarch64-sve.md
- The machine description file for AArch64 SVE, defining instruction patterns and properties used by the GCC compiler.