aarch64: umov and smov require base Advanced SIMD
AArch64 extension instructions `umov` and `smov` are now correctly guarded by `base_simd` attribute.
The AArch64 assembler instructions umov and smov, used for extending 16-bit values, were previously guarded by the fp (floating-point) architecture attribute. This commit corrects this by guarding them with the base_simd attribute instead. This ensures that code compiled without SIMD support (e.g., with -march=armv8-a+nosimd) will correctly fall back to memory-based extension, preventing assembler errors.
In Details
This change modifies the AArch64 machine description for SHORT extend patterns. The umov and smov alternatives, which are Advanced SIMD instructions, were incorrectly guarded by the fp attribute. This commit changes the guard to base_simd. Consequently, when SIMD is disabled (+nosimd), the assembler will now select memory-based extension alternatives instead of attempting to use unsupported SIMD instructions, thus avoiding assembler errors.
- umov
- An AArch64 instruction that moves a subset of a SIMD register to a general-purpose register.
- smov
- An AArch64 instruction that moves a subset of a SIMD register to a general-purpose register, preserving the other half.
- Advanced SIMD
- A set of single instruction, multiple data (SIMD) instructions on ARM processors, used for accelerated media and signal processing. Also known as NEON.
- base_simd
- An AArch64 architecture attribute indicating the presence of the base Advanced SIMD (NEON) instruction set.
- fp
- In the context of AArch64, this typically refers to the floating-point architecture extension.