aarch64: Allow zero register for CRC32 instructions to avoid moves.
aarch64 CRC32 instructions now accept the zero register directly, eliminating unnecessary moves for zero constants.
The AArch64 backend now permits the use of the zero register (wzr) for CRC32 instructions when an operand is a constant zero. This optimization avoids redundant mov instructions when initializing CRC values or providing zero data, simplifying generated code and potentially improving performance slightly.
In Details
The aarch64.md instruction patterns for CRC32 variants have been updated to include wzr as a valid operand for the initial CRC value and data inputs. This change removes the need for explicit mov wzr, #0 instructions when these inputs are zero constants, directly incorporating the zero register into the CRC instructions themselves.
- aarch64
- The 64-bit ARM architecture, widely used in mobile devices and increasingly in servers and desktops.
- CRC32 instructions
- Hardware instructions, available on some architectures like AArch64, that compute Cyclic Redundancy Check (CRC) checksums efficiently. They are often used for data integrity checks.
- zero register
- A special hardware register (e.g.,
wzron AArch64) that always reads as zero and writes to it are ignored. It simplifies code by providing a canonical source for the value zero. - register allocation
- The process by which the compiler assigns program variables and temporary values to hardware registers to minimize memory access and speed up computation.