AArch64 sqxtun instructions expressed as unsigned truncate of smax.
Simplifies AArch64 SIMD saturate and narrow instructions for better pattern matching.
The AArch64 sqxtun and related instructions are now represented using a simpler RTL structure: an unsigned truncate of a signed maximum against zero. This change allows the vectorizer to directly match these patterns, eliminating intermediate instructions and improving code generation efficiency for SIMD operations involving saturation and narrowing.
In Details
This commit refactors the RTL patterns for AArch64 SIMD instructions like sqxtun, sqxtun2, sqshrun, sqshrun2, sqrshrun, and sqrshrun2. The previous patterns used more complex RTL than necessary. They are rewritten to match us_truncate of smax against zero, which is the underlying operation. This ensures that the output from the vectorizer, particularly for expressions like MAX_EXPR <0, x>, can be directly recognized by the sqxtun pattern, eliminating extra movi and other instructions. Predicate removal of aarch64_simd_umax_half_mode and aarch64_simd_umax_quarter_mode…
- RTL
- Register Transfer Language, an intermediate representation used by GCC between the front-end and back-end. It represents operations on registers.
- sqxtun
- AArch64 SIMD instruction that performs signed to unsigned saturation and narrowing.
- us_truncate
- An RTL operation representing an unsigned truncate.
- smax
- An RTL operation representing a signed maximum.
- vectorizer
- A GCC optimization pass that identifies opportunities to replace scalar operations with equivalent SIMD (Single Instruction, Multiple Data) vector operations.