RISC-V: ARC-V RMX-100 load latency updated.
Updates load instruction latency for the ARC-V RMX-100 core.
The load instruction latency for the ARC-V RMX-100 processor has been updated. The previous latency value was considered a worst-case scenario, and the new value better reflects the likely case, potentially improving scheduling and performance. Additionally, the commit merges floating-point load instructions with general loads and updates branding information.
In Details
This commit adjusts the arcv_rmx100_load_insn definition in config/riscv/arcv-rmx100.md. The latency attribute for load operations has been modified from a higher, worst-case value to a lower, more typical value. This change aims to provide a more accurate performance model for the RMX-100 core. It also merges the floating-point load instruction (arcv_rmx100_fpload_insn) into the general load instruction definition, simplifying the machine description.
- load latency
- The number of clock cycles a processor takes from issuing a load instruction to when the data is available in a register.
- ARC-V
- A RISC-V based processor core architecture.
- RMX-100
- A specific processor core model within the ARC-V family.
- md
- Stands for 'machine description'. In GCC, .md files define the instruction set, patterns, and scheduling information for a target architecture.